Field
This disclosure relates generally to integrated circuits, and more specifically, to static state control in the integrated circuit during low power mode to address Bias Temperature Instability (BTI) ageing.
Related Art
Reliability of Metal-Oxide-Semiconductor (MOS) transistors becomes more critical as channel length continues to decrease. For these transistors, such as those with tenths of nanometers channel length, there are four common reliability issues, including high current injection (HCI), time dependent dielectric breakdown (TDDB), negative bias temperature instabilities (NBTI), and positive bias temperature instabilities (PBTI). Referring to both NBTI and PBTI, MOS transistors are affect by bias temperature instability (BTI) when they are biased with a direct-current (DC) voltage in their gate without a drain current (without a lateral electric field inside the channel). Generally, PBTI affects NMOS transistor while NBTI affects PMOS transistors.
During BTI stress, charges are trapped in the dielectric of the MOS gate, which makes the absolute value of the threshold voltage (Vth) increase. That is, the Vth of NMOS transistors is increased, and the Vth of PMOS transistors is decreased. Some part of this BTI degradation can be recovered when the stress is removed, therefore, BTI impact is more important during rest periods of a circuit as opposed to switching periods.
For example, FIG. 1 illustrates a clock distribution circuit 100 of an integrated circuit, which includes a chain of series connected inverters 104-114, and a NAND gate 102 which controls the switching of the inverter chain. When the enable signal, EN, at one input of NAND gate 102 is a logic level one, the inverter chain switches in accordance with an oscillating input, OSC, at another input of NAND gate 102. However, when EN is disabled, or a logic level zero, the logic values remain fixed, as illustrated in FIG. 1. That is the output of NAND gate 102 remains a logic level one, the output of inverter 104 remains a logic level zero, the output of inverter 105 remains a logic level one, and so on. Since an inverter is formed by a PMOS in series with an NMOS between power and ground, the PMOS transistor is stressed in those inverters with a 0 at the input (e.g. inverters 105, 107, 109, 111, and 113) while the NMOS transistor is stressed in those inverters with a 1 at the input (e.g. inverters 104, 106, 108, 110, 112, and 114).
The stress on the NMOS transistors result in an extra delay on the falling edge of the output of the inverter, and the stress on the PMOS transistors result in an extra delay on the rising edge of the output of the inverter. This results in deteriorating the clock duty cycle, resulting in errors in those circuits coupled to the output of clock distribution circuit 100. MOS transistors in any logic which becomes static suffer these BTI effects. Therefore, a need exists to balance BTI ageing of transistors so as to reduce failures in an integrated circuit.